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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P116
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75P116 is a version of the PD75116 in which the on-chip mask ROM is replaced by one-time PROM which can be written to once only. Since the PD75P116 is capable of program write by a user, it is suitable for evaluation in system development and limited production. Detailed functional descriptions are shown in the following User's Manual. Be sure to read for design purposes. PD751xx Series User's Manual : IEM-922
FEATURES * * * *
PD75116 compatible Program memory (PROM) capacitance : 16256 x 8 bits Data memory (RAM) capacitance : 512 x 4 bits Single power supply 5 V 10%
ORDERING INFORMATION
Ordering Code Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) Quality Grade Standard Standard 5
PD75P116CW PD75P116GF-3BE
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Note
There are no on-chip pull-up resistor and power-on reset function by means of a mask option.
The information in this document is subject to change without notice. The mark 5 shows major revised points.
Document No. IC-3358 (O. D. No. IC-7599A) Date Published February 1994 P Printed in Japan
(c) NEC Corporation 1994
PD75P116
PIN CONFIGURATION (TOP VIEW)
64-pin plastic shrink DIP (750 mil)
P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO P01/SCK P00/INT4 P123 P122 P121 P120 P133 P132 P131 P130 P143 P142 P141 P140 VPP VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS P90 P91 P92 P93 P80 P81 P82 P83 P70 P71 P72 P73 P60 P61 P62 P63 X1 X2 RESET P50 P51 P52 P53 P40 P41 P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3
PD75P116CW
2
PD75P116
64-pin plastic QFP (14 x 20 mm)
P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82
64 636261605958575655545352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3 VDD VPP P140 P141 P142 P143 P130
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 T11 T10 PTH00 PTH01
Pin Name P00 to P03 P10 to P13 P20 to P23 P30 P40 P50 P60 to to to to P33 P43 P53 P63 : Port 0 : Port 1 : Port 2 : : : : : : : : Port Port Port Port Port Port Port Port 3 4 5 6 7 8 9 12 m SCK SO SI PTO0, PTO1 PCL PTH00 to PTH03 INT0, INT1, INT4 INT2, INT3 TI0, TI1 X1, X2 RESET NC VDD VSS VPP MD0 to MD3 : : : : : : : : : : : : : : : : Serial Clock Serial Output Serial Input Programmable Timer Output Clock Output Programmable Threshold Input External Vectored Interrupt Input External Test Input Timer Input Clock Oscillation Reset No Connection Positive Power Supply Ground Programming Power Supply Mode Selection
P70 to P73 P80 to P83 P90 to P93 P120 to P123
P130 to P133 : Port 13 P140 to P143 : Port 14
P81 P80 P93 P92 P91 P90 VSS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02
PD75P116GF-3BE
3
PD75P116
OVERVIEW OF FUNCTIONS
Item Basic instructions Minimum instruction execution time ROM Internal memory RAM General register 512 x 4 4 bits x 8 x 4 banks (memory mapping) 3 types of accumulators corresponding to bit length of manipulated data * 1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA) Total 58 * CMOS input pins * CMOS input/output pins (LED direct drive capability) * Middle-high voltage N-ch open-drain input/output pins (LED direct drive capability) * Comparator input pins (4-bit precision) * 8-bit timer/event counter x 2 * 8-bit basic interval timer (watchdog timer applicable) * 8 bits * LSB-first/MSB-first switchable * Two transfer modes (transmit-receive/receive-only mode) 43 0.95 s, 1.91 s, 15.3 s (4.19 MHz operation) 3-stage switching capability 16256 x 8 Description
Accumulator
Input/output port
: 10 : 32 : 12 :4
Timer/counter
Serial interface
Vectored interrupt Test input Standby
External : 3, internal : 4 External : 2 * STOP/HALT mode * * * * Various bit manipulation instructions (set, reset, test, boolean operation) 8-bit data transfer, comparison, operation, increment/decrement instructions 1-byte relative branch instruction GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte
Instruction set
Operating temperature range Operating voltage Others
-40 to +85 C 5 V 10 % * Bit manipulation memory (bit sequential buffer : 16 bits) on-chip * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20mm)
Package
4
BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE PROM PROGRAM MEMORY 16256 x 8 BITS PROGRAM COUNTER (14) ALU SP(8) CY
BIT SEQ. BUFFER (16) PORT 0 PORT 1 BANK PORT 2 PORT 3 GENERAL REG. PORT 4 DECODE AND CONTROL 4 4 4 4 P20-P23 P30-P33 /MD0-MD3 P40-P43 4 4 P00-P03 P10-P13
PORT 5 RAM DATA MEMORY 512 x 4 BITS PORT 6 PORT 7
P50-P53 P60-P63
4 4
INTSIO
P70-P73
INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 INTERRUPT CONTROL fX / 2 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL CLOCK DIVIDER
N
PORT 8
4
P80-P83
PORT 9
4
P90-P93
PTH00-PTH03
4
CLOCK GENERATOR
STAND BY CONTROL
CPU CLOCK
PORT 12
4
P120-P123
PORT 13
4
P130-P133
PD75P116
PCL/P22
X1
X2
VPP VDD
VSS RESET
PORT 14
4
P140-P143
5
PD75P116
CONTENTS 1. PIN FUNCTIONS ....................................................................................................................................
1.1 1.2 1.3 1.4 1.5 PORT PINS ..................................................................................................................................................... OTHER PINS ................................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... RECOMMENDED CONNECTION OF PD75P116 UNUSED PINS ........................................................... NOTES ON USING P00/INT4 PIN AND RESET PIN ..................................................................................
7
7 8 9 10 10
2. 3.
DIFFERENCES BETWEEN PD75P116 AND PD75116 ...................................................................... 11 PROM (PROGRAM MEMORY) WRITE AND VERIFY .......................................................................... 12
3.1 3.2 3.3 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ................................................................... PROGRAM MEMORY WRITE PROCEDURE ................................................................................................ PROGRAM MEMORY READ PROCEDURE ................................................................................................. 12 13 14
4. 5. 6.
ELECTRICAL SPECIFICATIONS ............................................................................................................ 15 PACKAGE INFORMATION .................................................................................................................... 26 RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 28
APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 29 APPENDIX B. RELATED DOCUMENTATION ............................................................................................ 30
6
PD75P116
1. PIN FUNCTIONS
1.1 PORT PINS
Pin Name P00 P01 P02 P03 P10 P11
Input/Output Input Input/output Input/output Input
DualFunction Pin INT4 SCK SO SI
Function
8-bit I/O
After Reset
I/O Circuit Type *1 B
4-bit input port (PORT 0).
F Input E B x
INT0 INT1 Input INT2 INT3 PTO0 PTO1 Input/output PCL -- Input/output *2 Input E 4-bit input/output port (PORT 2). x 4-bit input port (PORT 1).
Input
B
P12 P13 P20 P21 P22 P23 P30 to P33
Input
E
Programmable 4-bit input/output port (PORT 3). MD0 to MD3 Input/output can be specified bit-wise. *2 4-bit input/output port (PORT 4). Data input/output pin for program memory (PROM) write/verify (low-order 4 bits). *2 4-bit input/output port (PORT 5). Data input/output pin for program memory (PROM) write/verify (high-order 4 bits). *2 Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise. *2 4-bit input/output port (PORT 7). 4-bit input/output port (PORT 8). 4-bit input/output port (PORT 9). *2 *2 *2
P40 to P43
Input/output
--
Input
E
P50 to P53
Input/output
--
Input
E
P60 to P63 P70 to P73 P80 to P83 P90 to P93
Input/output Input/output Input/output Input/output
Input
E
-- -- -- --
Input Input Input
E E E
P120-P123
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 12). +12 V withstand voltage. *2 N-ch open-drain 4-bit input/output port (PORT 13). +12 V withstand voltage. *2 N-ch open-drain 4-bit input/output port (PORT 14). +12 V withstand voltage. *2
Input
M-A
P130-P133
Input/output
--
Input
M-A
P140-P143
Input/output
--
--
Input
M-A
*
1. 2.
indicates Schmitt-triggered input. LED direct drive capability
7
PD75P116
1.2 OTHER PINS
Pin Name PTH00 to PTH03 TI0
Input/Output Input
DualFunction Pin --
Function Variable threshold voltage 4-bit analog input port. External event pulse input to timer/event counter. Or edge detection vectored interrupt input pin, or 1-bit input is also possible.
After Reset
I/O Circuit Type *1 N
Input TI1 PTO0 Input/output PTO1 SCK SO SI Input/output Input/output Input
--
B
P20 Timer/event counter output pin. P21 P01 P02 P03 Serial clock input/output pin. Serial data output pin. Serial data input pin. Edge detection vector interrupt input pin (detection of both rising and falling edges). Input Input Input F E B Input E
INT4
Input
P00
B
INT0 Input INT1 INT2 Input INT3 PCL Input/output
P10 P11 P12
Edge detection vector interrupt input pin (detection edge selectable).
B
Edge detection testable input pin (rising edge detection) P13 P22 Clock output pin System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. System reset input pin (low-level active). Mode selection pin for program memory (PROM) write/ verify. Positive power supply pin. Applies +6 V for write/verify. GND potential pin. Program voltage impression pin for program memory (PROM) write/verify. Connected to VDD directly in normal operation. Applies +12.5 V for PROM write/verify. Input Input
B
E
X1, X2
--
RESET MD0 to MD3 VDD VSS
Input Input/output
-- P30 to P33 -- --
B E
VPP *2
--
*
1. 2.
indicates Schmitt-triggered input. The device will not operate correctly unless VPP is connected to VDD directly in normal use.
8
PD75P116
1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75P116 are shown by in abbreviated form.
Type A VDD
Type F
data P-ch IN N-ch output disable Type D
IN/OUT
Type B
CMOS specification input buffer Type B
Input/output circuit made up to a Type D push-pull output and Type B Schmitt-triggered input. Type M-A IN/OUT data output disable N-ch (+12 V Withstand Voltage)
IN
Middle-High Voltage Input Buffer (+12 V Withstand Voltage) Schmitt-triggered input with hysteresis characteristic Type D VDD data Comparator P-ch OUT output disable N-ch VREF (Threshold Voltage) Push-pull output with high impedance output capability (P-ch and N-ch both OFF) Type E data Type D output disable IN + - Type N
IN/OUT
Type A This is an input/output circuit made up of a Type D push-pull output and Type A input buffer.
9
PD75P116
1.4 RECOMMENDED CONNECTION OF PD75P116 UNUSED PINS
Pin PTH00 to PTH03 TI0 TI1 P00 P01 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 Input status P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 Output status : Leave open. : Connect to VSS or VDD. Connect to VSS. Connect to VSS or VDD. Connect to VSS. Connect to VSS or VDD. Recommended Connection
1.5
NOTES ON USING P00/INT4 PIN AND RESET PIN
The P00/INT4 and RESET pins have a test mode setting function (for IC test) which tests internal operations of pin of the PD75P116 in addition to those functions given in 1.1 and 1.2. The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal operation, the test mode is engaged when noise greater than VDD is added, thus causing interference with normal operation. For example, this problem may occur if the P00/INT4 and RESET pins wiring is too long, causing line noise. To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the exterior add-on components shown in the Figures below.
q
Connect a Diode with Low VF (0.3 V max.) Between the VDD and the Pin.
VDD
q
Connect a Capacitor Between the VDD and the Pin.
VDD
Diode with low VF
VDD P00/INT4, RESET
VDD P00/INT4, RESET
10
PD75P116
2. DIFFERENCES BETWEEN PD75P116 AND PD75116
The PD75P116 is a product in which the program memory (mask ROM) of the PD75116 is changed to a user programmable PROM. Other functions of the PD75P116 and PD75116 are virtually the same only with the differences shown in Table 2-1. For details of CPU functions and on-chip hardware, see the "PD75116 User's Manual" (IEM-922). Table 2-1 Differences between PD75P116 and PD75116
Item Program memory
5
PD75116
Mask ROM
PD75P116
One-time PROM 0000H-3F7FH (16256 x 8 bits) 0000H-01FFH (512 x 4 bits) No 5 V 10 % VPP
Data memory Pull-up resistor (ports 12 to 14) Power-on reset function Operating voltage range 31 pins (SDIP) Pin function 57 pins (QFP) 33 to 36 pins (SDIP) 59 to 62 pins (QFP) Electrical specification Other P33/MD3 to P30/MD0
Mask option 2.7 to 6.0 V NC
P33 to P30
Different consumption current, operating temperature range, etc. Refer to the electrical specifications parameters for each data sheet for details. Different noise resistance, noise radiation, etc., due to difference in the size of circuits and mask layout.
Note
The PROM and ROM products differ in noise resistance and noise radiation. If you are considering replacement of the PROM products by the mask ROM product in the transition from preproduction to volume production, this should be thoroughly evaluated with the mask ROM CS product (not ES product).
11
PD75P116
3. PROM (PROGRAM MEMORY) WRITE AND VERIFY
The ROM built into the PD75P116 is a 16256 x 8-bit PROM. The pins shown in the table below are used to write/verify this PROM. There is no address input; instead, a method to update the address by the clock input from the X1 pin is adopted.
Pin Name VPP
Function Voltage application pin for program memory write/verify (normally VDD potential). Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. Operating mode selection pin for program memory write/ verify.
X1, X2
MD0 to MD3
P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. VDD Supply voltage application pin. Applies 5 V 10 % in normal operation, and 6 V for program memory write/verify.
Note 3.1
Since the PD75P116 is a one-time PROM version, UV-ray erasure is not possible. PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
The PD75P116 assumes the program memory write/verify mode is +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. The rest of pins are all set at the VSS potential by the pull-down resistor.
Operating Mode Setting Operating Mode VPP VDD MD0 H L +12.5 V +6 V L H L x H H H H Verify mode Program inhibit mode MD1 L H MD2 H H MD3 L H Program memory address zero-clear Write mode
x : L or H
12
PD75P116
3.2 PROGRAM MEMORY WRITE PROCEDURE
The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) Supply +5 V to the VDD and VPP pins. (3) 10 s wait. (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP. The program inhibit mode. Write data in the 1-ms write mode. The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (Number of times written in (7) to (9): X) x 1-ms additional write. The program inhibit mode. Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address. The program memory address 0 clear mode. Change the VDD and VPP pins voltage to +5 V.
(16) Power off. The diagram below shows the procedure of the above (2) to (12).
Repeated X Times
Write
Verify
Additional Write
Address Increment
VPP VPP VDD VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Input
Data Output
Data Input
MD0
MD1
MD2
MD3
13
PD75P116
3.3 PROGRAM MEMORY READ PROCEDURE The PD75P116 can read the content of the program memory in the following procedure. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) (3) (4) (5) Supply +5 V to the VDD and VPP pins. 10 s wait. The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP.
(6) The program inhibit mode. (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) The program inhibit mode. (9) The program memory address 0 clear mode. (10) Change the VDD and VPP pins voltage to +5 V. (11) Power off. The diagram below shows the procedure of the above (2) to (9).
VPP VPP VDD
VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Output
Data Output
MD0
MD1
"L"
MD2
MD3
14
PD75P116
4. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Supply voltage Supply voltage Input voltage Output voltage
SYMBOL VDD VPP VI1 VI2 *1 VO
TEST CONDITIONS
RATING -0.3 to + 7.0 -0.3 to 13.5
UNIT V V V V V mA mA mA mA mA mA mA mA C C
Except ports 12 to 14 Ports 12 to 14
-0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3
1 pin Output current high IOH Total pins Peak value 1 pin Ports 0, 2 to 4, 12 to 14 total Ports 5 to 9 total Operating temperature Storage temperature Topt Tstg Effective value Peak value Effective value Peak value Effective value
-15 -30 30 15 100 36 100 36 -40 to +85 -65 to +125
Output current low
IOL*2
*
1. 2.
The power supply impedance (pull-up resistor) should be 50 k or more when the voltage exceeding 10 V applied to ports 12, 13 and 14. Effective value should be calculated as follows: [Effective value] = [Peak value] x
duty
Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
15
PD75P116
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = -40 to +85 C, VDD = 5 V 10 %)
RESONATOR
RECOMMENDED CIRCUIT
X1 X2
PARAMETER Oscillator frequency (fXX) *1
TEST CONDITIONS
MIN.
TYP.
MAX. *3 5.0
UNIT
2.0 VDD =
MHz
Ceramic resonator
C1
C2
Oscillation stabilization time *2 Oscillator frequency (fXX) *1
After VDD reaches 4.5 V.
4
ms
X1
X2
2.0
4.19
*3 5.0
Crystal resonator
C1 C2
MHz
Oscillation stabilization time *2 X1 input frequency (fX) *1 X1 input high/low level width (tXH , tXL)
After VDD reaches 4.5 V.
10 *3 5.0
ms
X1
X2
2.0
MHz
External clock
PD74HCU04
100
250
ns
*
1. 2.
5
3.
Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. or STOP mode release. When the oscillator frequency is 4.19 MHz < fXX < 5.0MHz, PCC = 0011 should not be selected as - instruction execution time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 s, with the result that the specified MIN value of 0.95 s cannot be observed.
5
Note
When the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. * Keep the wiring as short as possible. * Do not cross any other signal lines. * Keep away from lines in which a high fluctuating current flows. * Ensure that oscillator capacitor connection points are always at the same potential as VSS. Do not ground in a ground pattern in which a high current flows. * Do not take a signal from the oscillator.
16
PD75P116
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 5 V 10 %)
PARAMETER
SYMBOL VIH1 VIH2 VIH3 VIH4 VIL1
TEST CONDITIONS Other than below Ports 0 & 1, TI0 & 1, RESET Ports 12 to 14 X1, X2 Other than below Ports 0 & 1, TI0 & 1, RESET X1, X2 IOH = -1 mA IOL = 15 mA Ports 0, 2, to 9 Ports 12 to 14
MIN. 0.7VDD 0.8VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0
TYP.
MAX. VDD VDD 12 VDD 0.3VDD 0.2VDD 0.4
UNIT V V V V V V V V
Input voltage high
Input voltage low
VIL2 VIL3
Output voltage high
VOH
0.55 0.35
2.0 2.0 0.4
V V V
Output voltage low
VOL
IOL = 10 mA IOL = 1.6 mA
ILIH1 Input leakage current high VIN = VDD ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 12 V VOUT = 0 V 4.19 MHz Crystal oscillation C1 = C2 = 22 pF VIN = 12 V
Other than below X1, X2 Ports 12 to 14 Except X1 & X2 X1, X2 Other than below Ports 12 to 14
3 20 20 -3 -20 3 20 -3
A A A A A A A A
mA
IDD1 Power supply current *1 IDD2 IDD3
VDD = 5 V 5 % *2 HALT mode*3 VDD = 5 V 5 %
5 500 0.5
10 1500 20
A A
STOP mode, VDD = 5 V 5 %
*
1. 2. 3.
Not including current flowing in comparator. When processor clock control register (PCC) is set to 0011 operating in high-speed mode. When PCC is set to 0100 and CPU is halted in HALT mode.
17
PD75P116
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance
SYMBOL CIN COUT CIO
TEST CONDITIONS
MIN.
TYP.
MAX. 15
UNIT pF pF pF
f = 1 MHz Unmeasured pins returned to 0 V.
15 15
COMPARATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 5 V 10 %)
PARAMETER Comparison accuracy Threshold voltage PTH input voltage Comparator circuit current consumption
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. 100
UNIT mV V V mA
VACOMP VTH VIPTH
PTHM7 set to "1" 0 0 1
VDD VDD
18
PD75P116
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER CPU clock cycle time* (minimum instruction execution time = 1 machine cycle) TI input frequency TI input high/low-level width SCK cycle time SYMBOL TEST CONDITIONS VDD = 4.75 to 5.5 V tCY 1.1 fTI tTIH, tTIL tKCY tKH, SCK high/low-level width tKL SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK INT0 to INT4 high/lowlevel width RESET low level width tSIK tKSI tKSO tINTH, tINTL tRSL 5 5 Output tKCY/2-50 100 400 300 ns ns ns ns Input Output Intput 0.8 0.95 0.4 0 0.48 32 1 MIN. 0.95 TYP. MAX. 32 UNIT
s s
MHz
s s s s
s s
*
The cycle time of the CPU clock () is determined by the oscillator frequency of the connected resonator and the processor clock control register (PCC). The graph on the below shows the cycle time tCY characteristics against supply voltage VDD.
Relation between Cycle Time and Supply Voltage
tCY vs. VDD
5
Operating Guaranteed Range
Cycle Time tCY [s]
10
5
1
0.5 0 1 2 3 4 5 Supply Voltage VDD [V] 6
Note tCY vs. VDD characteristics are different from those of the PD75P108 19
PD75P116
AC Timing Test Point (Excluding ports 0 & 1, TI0, TI1, X1, X2, RESET)
0.7 VDD 0.3 VDD
Test Points
0.7 VDD 0.3 VDD
Clock Timing
1/fX
tXL
tXH VDD - 0.5 0.4
X1 Input
TI Input Timing
1/fTI
tTIL TI0, TI1
tTIH 0.8 VDD 0.2 VDD
20
PD75P116
Serial Transfer Timing
tKCY tKL SCK tKH 0.8 VDD 0.2 VDD tSIK SI tKSI 0.8 VDD Input Data 0.2 VDD
tKSO SO Output Data
Interrupt Input Timing
tINTL INT0-INT4 0.8 VDD 0.2 VDD
tINTH
RESET Input Timing
tRSL
RESET
0.2 VDD
21
PD75P116
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +85 C)
PARAMETER Data retention supply voltage Data retention power supply current *1 Release signal set time Oscillation stabilization wait time *2 SYMBOL VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt request VDDDR = 2.0 V 0 217/fx *3 TEST CONDITIONS MIN. 2.0 0.1 TYP. MAX. 5.5 10 UNIT V
A s
ms ms
*
1. 2. 3.
Does not include current flowing in the comparator. The oscillator stabilization wait time is the time during which CPU operation is halted to prevent unstable operation when oscillation begins. Depends on the setting of the basic interval timer mode register (BTM) (table below).
BTM3 BTM2 BTM1 BTM0 - - - - 0 0 1 1 0 1 0 1 0 1 1 1 WAIT Time (Figure in Parentheses is for fXX = 4.19 MHz) 220/fXX (Approx. 250 ms) 217/fXX (Approx. 31.3 ms) 215/fXX (Approx. 7.82 ms) 213/fXX (Approx. 1.95 ms) Internal RESET Operation HALT Mode Operating Mode
Data Retention Timing (STOP Mode Release by RESET)
STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution tSREL
RESET tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode Operating Mode
STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT tSREL
22
PD75P116
DC PROGRAMMING CHARACTERISTICS (Ta = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Input voltage high VIH2 VIL1 Input voltage low VIL2 Input leakage current Output voltage high Output voltage low VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH X1, X2 Except X1 & X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 VDD-0.5 0 0 VDD 0.3 VDD 0.4 10 V V V SYMBOL VIH1 TEST CONDITIONS Except X1 & X2 MIN. 0.7VDD TYP. MAX. VDD UNIT V
A
V V mA mA
Note 1. 2.
Ensure that VPP does not reach +13.5 V or above including overshot. Ensure that VDD is applied before VPP and cut off after VPP.
23
PD75P116
AC PROGRAMMING CHARACTERISTICS (Ta = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Address setup time *2 (to MD0) MD1 setup time (to MD0) Data setup time (to MD0) Address hold time *2 (from MD0) Data hold time (from MD0) Data output float delay time from MD0 VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) Data output delay time from MD0 MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-/low-level width X1 input frequency Initial mode setting time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Data output delay time from address *2 Data output hold time from address *2 MD3 hold time (from MD0) Data output float delay time from MD3 SYMBOL tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR *1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- -- In program memory read In program memory read In program memory read In program memory read In program memory read 2 2 2 2 2 0 2 2 130 MD0 = MD1 = VIL tM1H + tM1R > 50 s - 2 2 10 0.125 4.19 TEST CONDITIONS MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 1 1.0 1.05 21.0 130 TYP. MAX. UNIT
s s s s s
ns
s s
ms ms
s s s s s s
MHz
s s s s s
ns
s s
*
1. 2.
Corresponding to PD27C256 symbol. Internal address signal is incremented by 1 on rise of 4th X1 input, and is not connected to a pin.
24
PD75P116
Program Memory Write Timing
tVPS
VPP VPP VDD tVDS tXH
VDD + 1 VDD VDD X1
Data Output
P40-P43 P50-P53 t1 MD0
tXL
Data Input Data Input Data Input
tDS tOH tM1R
tDV
tDF
tDS
tDH tAH
tAS
tPW MD1 tPCR MD2 tM3S MD3 tMIS tM1H
tOPW tMOS
tM3H
Program Memory Read Timing
tVPS
VPP VPP VDD tVDS tXH
VDD + 1 VDD VDD X1 tXL
tDAD tHAD
P40-P43 P50-P53 t1 MD0
Data Output
Data Output
tDFR tDV tM3HR
MD1
"L" tPCR
MD2 tM3SR MD3
25
PD75P116
5. PACKAGE INFORMATION
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J
I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
26
PD75P116
64 PIN PLASTIC QFP (14x20)
A B
5
51 52
33 32
detail of lead end
C
D
S
Q R
64 1
20 19
F G
H
I
M
J
K P N L M
NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05
INCHES 0.9290.016 0.795 +0.008 -0.009 0.551+0.009 -0.008 0.6930.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003
0.10 0.004 2.7 0.106 0.10.1 0.0040.004 55 55 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2
27
PD75P116
5
6. RECOMMENDED SOLDERING CONDITIONS
The PD75P116 should be mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 6-1 Surface Mount Type Soldering Conditions
PD75P116GF-3BE : 64-pin plastic QFP (14 x 20 mm)
Soldering Method Soldering Conditions Package peak temperature: 230C, Duration: 30 sec. max. (at 210C or above), Number of times: Once Time limit: 2 days* (thereafter 16 hours prebaking required at 125C) Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: Once Time limit: 2 days* (thereafter 16 hours prebaking required at 125C) Solder bath temperature: 260C max., Duration: 10 sec. max Number of times: Once Preheating temperature: 120C max. (package surface temperature), Time limit: 2 days* (thereafter 16 hours prebaking required at 125C) Pin part temperature: 300C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol
Infrared reflow
IR30-162-1
VPS
VP15-162-1
Wave soldering
WS60-162-1
Pin part heating
--
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% 1H. Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 6-2 Insertion Type Soldering Conditions
Note
PD75P116CW : 64-pin plastic shrink DIP (750 mil)
Soldering Method Wave Soldering (lead part only) Pin part heating Soldering Conditions Solder bath temperature: 260C max., Duration: 10sec. max. Pin part temperature: 260C max., Duration: 10sec. max.
Note
Ensure that the application of (wave soldering) is limited to the lead part and no solder touches the main unit directly.
Notice A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (230 C), number of times: twice, relaxation of time limit, etc.), contact NEC sales personnel.
28
PD75P116
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75P116.
IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 EP-75108CW-R Hardware EP-75108GF-R EV-9200G-64 PG-1500 PA-75P108CW PA-75P116GF Software IE control program PG-1500 controller RA75X relocatable assembler
In-circuit emulator for 75X series Emulation board for IE-75000-R and IE-75001-R Emulation probe for PD75P116CW Emulation probe for PD75P116GF A 64-pin conversion socket EV-9200G-64 is provided. PROM programmar This is a PROM programmar adapter for PD75P116CW and connects to PG-1500. This is a PROM programmar adapter for PD75P116GF and connects to PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A *3) * IBM PC/ATTM series (PC DOSTM Ver.3.1)
*
1 2 3
Maintenance product This is not incorporated in the IE-75001-R. A task swap function is provided with Ver.5.00/5.00A; however, a task swap function cannot be used with this software. For development tools manufactured by a third pary, see the "75X Series Selection Guide" (IF-151).
Remarks
29
PD75P116
5 APPENDIX B. RELATED DOCUMENTATION
List of Device-Related Documents
Document Name User's Manual Instruction Application Table (I) Introductory Volume Application Note (II) Remote-Controlled Reception Volume (III) Bar-Code Reader-Volume (IV) IC Control for MSK Transmission/Reception Volume 75X Series Selection Guide Document No.
List of Development Tool Related Documents
Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75108CW-R User's Manual EP-75108GF-R User's Manual PG-1500 User's Manual Software Operation Volume RA75X Assembler Package User's Manual Language Volume PG-1500 Controller User's Manual Document No.
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcomputer Related Product Guide Other Manufacturer Volume Document No.
Note
The above related documents may be changed without notice. Be sure to use the latest documents for design purposes.
30
PD75P116
[MEMO]
31
PD75P108B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.

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